1. Field of the Invention
The present invention generally relates to a transcurrent circuit, and more particularly, to a transcurrent circuit forming a part of an electronic circuit generally used in electronic devices.
2. Description of the Related Art
Recently, in integrated circuits (ICs) used for miniaturization and power reduction of electronic devices, particularly, an integrated circuit (IC) manufactured in a process using a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is widely used. Further, in these electronic circuits constructed with transistors, a transcurrent circuit and a current mirror circuit, which produce a current output determined by a specified transient function from a current input, are known.
When manufacturing the integrated circuit, it is difficult to form each device element at precise absolute characteristic values, but it is significantly easy to precisely determine a relative value between the characteristics of the device elements. Using the above-discussed feature of the integrated circuit, in a transcurrent circuit such as a current mirror circuit, miniaturization of the circuit forming area and reduction of the circuit power consumption are required.
FIG. 1 shows a schematic diagram of a prior art transcurrent circuit. In FIG. 1, a basic circuit of a transcurrent circuit 11 is shown. In the transcurrent circuit 11, a drain of a transistor M1 (for example, an N-channel MOSFET) is connected to a first power source 12, and a source thereof is connected to an earth ground (GND) as a second power source. Further, a gate of the transistor M1 is connected to the drain of itself. The transistor M1 is specified by a ratio of a gate width W.sub.1 to a gate length L.sub.1 (W.sub.1 /L.sub.1).
On the other hand, a drain of a transistor M2 of an N-channel MOSFET is connected to a third power source 13, and a source thereof is connected to the GND. Further, a gate of the transistor M2 is connected to the gate of the transistor M1. The transistor M2 is specified by a ratio of a gate width W.sub.2 to a gate length L.sub.2 (W.sub.2 /L.sub.2).
In this case, the gate width W.sub.2 of the transistor M2 is designed to be the same as the gate width W.sub.1 of the transistor M1, and the gate length L.sub.2 is designed to be the same as n times the gate length L.sub.1 of the transistor M1. Therefore, the ratio (W.sub.2 /L.sub.2) in the transistor M2 is represented by a ratio (W.sub.1 /nL.sub.1).
In the transcurrent circuit 11, when a drain current I.sub.1 flows into the transistor M1 on an input stage, a voltage is applied to the drain of the transistor M2 on an output stage, and a current I.sub.2 as an output current flows through the transistor M2.
FIG. 2A shows a top plane view of a layout pattern of the transistor M1 in the integrated circuit shown in FIG. 1, and FIG. 2B shows a top plane view of a layout pattern of the transistor M2 in the integrated circuit. At the transistor M1 and the transistor M2 shown in FIG. 2A and FIG. 2B, a drain (D) region, a gate (G) region, and a source (S) region are formed on the wafer at a given distance interval.
As discussed above, the gate length and the gate width of the transistor M1 are respectively designed to be L.sub.1 and W.sub.1. For the transistor M2, the gate length and the gate width thereof are designed to be L.sub.2 (=nL.sub.1) and W.sub.2 (=W.sub.1). For the transistors M1, M2, a ratio of current transform (I.sub.2 /I.sub.1) is changed by the gate length and the gate width.
Namely, a current transform ratio R1 (=I.sub.2 /I.sub.1) in the transcurrent circuit 11 is represented by the following equation. ##EQU1##
The above equation is represented using each gate length and each gate width as follows: EQU R1=(W.sub.1 /nL.sub.1).times.(L.sub.1 /W.sub.1)=1/n
For example, for achieving a current ratio I.sub.1 :I.sub.2 =1:2, the gate widths of the transistors M1, M2 are set to be the same and the gate length of the transistor M1 is set to be 2L.sub.1 (namely, n=2).
Since the circuit forming area of the transcurrent circuit needs to be reduced, the gate lengths of the transistors M1, M2 are designed as small as possible, for example, to be less than 1 .mu.m, which is substantially the minimum value with present manufacturing techniques.
FIG. 3 shows a schematic diagram of a current-voltage transforming circuit using the prior art transcurrent circuit. A current-voltage transforming circuit 21 shown in FIG. 3 is constructed with a transcurrent circuit 22 and a voltage transforming circuit 23.
In the transcurrent circuit 22, a source (S) of a transistor M3 of a P-channel MOSFET is connected to a first power source 24, and a drain (D) thereof is connected to an earth ground (GND) as a second power source through a current source 25.
Further, a source (S) of a transistor M4 of a P-channel MOSFET is connected to the first power source 24, and a drain (D) thereof is connected to the earth ground (GND) as the second power source through a current source 26. In addition, gates (G) of the respective transistors M3, M4 are connected to each other, and the gates (G) is also connected to the drain (D) of the transistor M3.
On the other hand, in the voltage transforming circuit 23, a source (S) of a transistor M5 of a P-channel MOSFET is connected to the first power source 24, and a drain (D) thereof is connected to the earth ground (GND) as the second power source through a current source 27. Further, a gate of the transistor M5 is connected to the drain (D) of the transistor M4. Also, from a drain (D) of the transistor M5, an output voltage V.sub.0 is produced.
In this case, the transistors M3 and M4 have the same gate width W.sub.1 and gate length nL.sub.1, and the transistor M5 has the gate width W.sub.1 and the gate length L.sub.1. Therefore, currents I.sub.3 and I.sub.4 flowing through the current sources 25 and 26 are set to be the same (I.sub.3 =I.sub.4).
In this configuration, when the current I.sub.3 (and I.sub.4) flowing from the current sources 25, 26 into the transistors M3, M4 is flexibly changed a little, a drain voltage of the transistor M4 also varies. When the variation of the drain voltage of the transistor M4 is applied to the gate of the transistor M5, a voltage amplitude V.sub.0 is obtained from the drain (D) of the transistor M5.
In this case, when each voltage at the connection nodes comes close to the voltage of each power source, the voltage amplitude V.sub.0 may decrease. Therefore, in order to prevent the voltage amplitude V.sub.0 from decreasing, a ratio of current values flowing the current paths needs to be maintained.
Namely, so as to maintain the following relationship (2), the gate widths and the gate lengths of the respective transistors M3 to M5 need to be designed. ##EQU2##
FIG. 4A and FIG. 4B show illustrations for explaining a principle of voltage transformation in the current-voltage transforming circuit 21 shown in FIG. 3. FIG. 4A shows a conventional amplifier circuit using a MOSFET M0. In FIG. 4A, a resistor R is connected to a drain of the transistor M0. When an input voltage V.sub.in is applied to a gate of the transistor M0, a drain current I.sub.D is represented by an equation I.sub.D =g.sub.m V.sub.in (g.sub.m is conductance of the transistor M0, and the drain current I.sub.D is obtained as a voltage through the resistor R.
In this case, since an output voltage V.sub.out is determined by an equation V.sub.out =I.sub.D .times.R=g.sub.m .times.V.sub.in .times.R, an amplifying ratio (amplifier gain) is represented by V.sub.out /V.sub.in =g.sub.m .times.R. In the integrated circuit, a value of the resistor R may not be increased enough, because a large forming area is required for the resistor. Therefore, in the circuit shown in FIG. 4A, the amplifying ratio cannot be obtained much.
In the circuit shown in FIG. 4B, a current source 28 constructed with a transistor is provided instead of the resistor R as compared to the circuit shown in FIG. 4A. Using an internal resistor R.sub.ds of the current source 28, in the same way as shown in FIG. 4A, the output voltage V.sub.out is produced. In this case, the amplifying ratio is represented by V.sub.out /V.sub.in =g.sub.m .times.R.sub.ds. As discussed above, the current source 28 is constructed with the transistor. Therefore, the internal resistor R.sub.ds may be formed as a relatively large value, and, thus, the amplifying ratio may be increased.
Returning to FIG. 3, when the current flowing from the current sources 25, 26 is slightly changed, the gate voltage V.sub.GS of the transistor M5 changes, and the drain current flows from the transistor M5. When an internal resistor of the current source 27 is formed as a large value, the amplifying ratio of the voltage transforming circuit 23 may be increased. As a result, a large variation of the output voltage V.sub.0 may be obtained.
However, in the above-discussed transcurrent circuit 11 shown in FIG. 1 and current-voltage transforming circuit 21 shown in FIG. 3, when the gate lengths of the transistors M1 to M5 of the MOSFETs vary, a threshold voltage also changes due to the short channel effect. As a result, the above-discussed equations (1) and (2) may not be defined.
In general, when the layout patterns are formed on the wafer, dispersion of the gate length and the gate width occurs due to imperfect mechanical precision. When a deviation of the gate length due to the dispersion is represented by a symbol ".delta.", the current transform ratio in the transcurrent circuit 11 shown in FIG. 1 is shown in the following equation (3). ##EQU3##
Further, the current transform ratio in the current-voltage transforming circuit 21 shown in FIG. 3 is shown in the following equation (4). ##EQU4##
Therefore, there is a problem in that it is very difficult to achieve a desired current transform ratio due to dispersion of the gate length which occurred in the pattern forming process.
Further, in order to reduce an influence from the dispersion of the gate length which occurs in the pattern forming process, some methods can be used for obtaining a large current transform ratio. For example, a first method is to increase the gate length, and a second method is changing the gate width while maintaining the gate length at the same value. However, the methods of increasing the gate length or the gate width cause the gate region to increase. Therefore, there is a problem in that methods as reducing of the circuit forming area may not be achieved.